Dr. J V R Ravindra

Department:
Electronics & Communication Engineering
Faculty Id:
VCE 370
Designation:
Principal & Professor
Years of Experience:
14 years
Employment Status:
Full Time – Ratified by JNTUH
Phone:

Date of Birth:

10 August , 1977

Areas of Specialization :

Modeling of Ultra Low power Interconnects, High-Speed, and Low power Arithmetic Circuits, Low Power DSP Architectures, Hardware Security, Wireless Sensor Networks.

 

Qualification:

Ph.D. in Electronics and Communication Engineering, IIIT-H, Hyderabad,
PG Degree in M. E (System and Signal Processing), 2003, Osmania University, Hyderabad,
UG Degree in B. E (Elec. & Comm. Engg.),1999,Osmania University, Hyderabad.

Subjects Taught:

Basic Electrical Engineering, Signals and Systems, Digital Signal Processing, Probability & Stochastic Process, VLSI Design, Electromagnetic Theory & Transmission Lines, Digital Logic Design, Electronic Devices and Circuits

Papers Published:

Journals:

  1. AkshithaVuppala, R Sai Roshan, Shaik Nawaz, JVR Ravindra, “An Efficient Optimization and Secured Triple Data Encryption Standard Using Enhanced Key Scheduling Algorithm” Journal of Procedia Computer Science, Elsevier, 1054-1063, Jan 2020.
  2. B.Srikanth, M. Siva Kumar, JVR. Ravindra and K. Hari Kishore, “The Enhancement of Security Measures in Advanced Encryption Standard using Double Precision Floating Point Multiplication Model” Transactions on Emerging Telecommunications Technologies, Wiley, pp. 1-13, June 2020
  3. R. Phani Vidyadhar, P. Ganga Kiran, E. Pranavi, J. Ashwitha, JVR Ravindra, “Noninvasive Design of Low Cost Foot Therapy Bot for Plantar Fasciitis”, International Journal of Advanced Trends in Computer Science and Engineering, World Press publications, pp. 2871-2875, June 2020.
  4. M. Rajesh, JVR Ravindra, “Design of Low Power and High speed Charge Sharing Differential Voltage Comparator using Small Swing Domino Logic”, International Journal of Advanced Trends in Computer Science and Engineering, World Press Publications, pp. 2893-2898, June 2020
  5. B. Srikanth, M. Siva Kumar, J.V.R. Ravindra, , K. Hari Kishore “Double Precession Floating Point Multiplier using Schonhage – Strassen Algorithm used for FPGA Accelerator” in International Journal of Emerging Trends in Engineering Research, Volume 7, No. 11, pp. 677-684, Nov 2019.
  6. Sangeeta Singh, J.V.R. Ravindra, B.RajendraNaik, “Power and Area Optimized FRA-CSLA for High-Speed NoC Applications” International Journal of Advanced Trends in Computer Science and Engineering, Vol. 8, No. 3, pp. 883-888, May 2019.
  7. Lavanya Maddisetti, Ranjan K. Senapati, Ravindra JVR, “Supervised Machine Learning for Training a Neural Network as 5:2 Compressor” in International Journal of Innovative Technology and Exploring Engineering (IJITEE), Vol. 8 No.10, Aug 2019.
  8. Lavanya Maddisetti, Ranjan K. Senapati , JVR Ravindra, “Training Neural Network as Approximate 4:2 Compressor applying Machine Learning Algorithms for Accuracy Comparison”, International Journal of Advanced Trends in Computer Science and Engineering, Vol. 8, No.2 pp. 211-215, Mar 2019.
  9. Lavanya Maddisetti, Ranjan K. Senapati , JVR Ravindra “Low-Power Near-Explicit 5:2 Compressor for Superior Performance Multipliers” in International Journal of Engineering Research and Technology.  Vol 11, No. 4,  529-545, April. 2018.
  10. Ch. Ashok Babu, JVR Ravindra and K.Lalkishore, “Design of ALU system using Proposed PMOS and NMOS for low power and high speed applications,” International Journal of Engineering & Technology (IJET), vol.7, no. 2, pp.498-504, 2018.
  11. B. Srikanth, Dr. M. Siva Kumar ,Dr. K. Hari Kishore, Dr. J.V.R. Ravindra “Towards reducing area and power of a multiplier with double precision floating point computations using FPGA accelerators” , Journal of Advanced Research in Dynamical and Control Systems, 9(18):2780-2789, Jan 2017.
  12. Ch. Ashok Babu, JVR Ravindra and K.Lalkishore, “Design Of Proposed Universal Gates for Low Power Applications” PentaGram International Conference 2017.
  13. Ch. Ashok Babu, JVR Ravindra and K.Lalkishore, “Design of ultra-low power PMOS and NMOS for Nano scale VLSI circuits,” International Journal of Scientific research circuits and systems (IJSRCS), vol.5, No.14, 2015.
  14. Ch. Ashok Babu, JVR Ravindra and K.Lalkishore, “Design of high drive BICMOS inverter and NAND gate for low power applications,” International Journal of advances in engineering research (IJAER), vol.7, no. 3, pp.19-27, March , 2014.
  15. Ch. Ashok Babu, JVR Ravindra and K.Lalkishore, “An adder with Proposed PMOS and NMOS for ultra lower power applications in deep submicron technology,” Global Journal of Research Engineering (GJRE), vol.13, no.14, 2013.
  16. Ch. Ashok Babu, JVR Ravindra and K.Lalkishore, “Proposed circuit level leakage power reduction technique for ultra low power and high speed VLSI circuits,” International Journal of Communication Engineering Applications (IJCEA), vol.3 no.3, pp. 508-514, December, 2012.
  17. Ch. Ashok Babu, J.V.R.Ravindra, K.Lal Kishore, “Novel Circuit Level Leakage Power Reduction Technique for Ultra Low Power and High Speed VLSI Circuits” in International Journal of Communication Engineering Applications (IJCEA). Vol. 3, No. 3, Aug-Dec 2012.
  18. J.V.R.Ravindra, M.B.Srinivas, “Model Order Reduction of Linear Time Variant High Speed VLSI Interconnects using Frequency Shift Technique” in International Journal of Electronics, Circuits and Systems, World Academy Publishers. Vol. 8, pp.772-776, 2008.
  19. J.V.R.Ravindra, M.B.Srinivas, “Delay And Energy Efficient Coding Technique For Capacitive Interconnects” in special issue on Advances in Circuits and Systems for Large Scale Integration in The Journal of Circuits, Systems, and Computers (JCSC). Vol. 16, No. 6 (2007), pp. 929-942.

 

Conferences

  1. Vaishnavi Reddy Mandadi, Sai Pooja Reddy Nadimpally and JVR Ravindra, “UBAPS: Inexact Unsigned Binary 5:2 Compressor towards Power Efficient and High Speed for 3-stage FIR Filter”       4th International Conference on Inventive Communication and Computational Technologies, India, 2020  (Accepted)
  2. Rishi kiran, Swathivangala, JVR Ravindra, “PERAM: Ultra Power Efficient Array Multiplier using Reversible Logic for High Performance MAC” in proceedings of  4th International Conference on Inventive Communication and Computational Technologies. 2020.
  3. Thanmai T, JVR Ravindra, “High Performance, Low Power Architecture of 5-stage FIR Filter using Modified Montgomery Multiplier’ in proceedings of IEEE 25th International Conference on Applied Electronics 2020 (AE 2020). CZ
  4. Sai Roshan Rangavajjala, Nawaz Shaik, AkshithaVuppala and JVR Ravindra, “Ultra Power Efficient Melior Quantum Multiplier with Reduced Ancilla and Garbage Outputs” in proceedings of 3rd International Conference On Computing and Communication Systems (I3CS 2020)
  5. Santhosh Reddy Gangilla, Sai Vandana Kala, S V R Subramanya Sai and JVR Ravindra, “Efficient Design of MISTO CDL Adder Cell for High Throughput and Power-Efficient Array Divider” ICSCSP20: Springer 3rd International Conference on Soft Computing and Signal Processing 2020.
  6. Rishi kiran, Swathivangala, JVR Ravindra, “QUEST: Quantum Computing based Reversible Hybrid Encoder/ Decoder for Error Resilient Transmission” in proceedings of ICSCSP20: Springer 3rd International Conference on Soft Computing and Signal Processing 2020.
  7. LavanyaMaddisetti ; JVR Ravindra, “Low-Power. High-Speed Adversarial Attack based 4:2 Compressor as Full Adder for Multipliers in FIR Digital Filters”, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, 2019.
  8. LavanyaMaddisetti ; JVR Ravindra, ‘Machine Learning Based Power Efficient Approximate 4:2 Compressors for Imprecise Multipliers” in proceedings of 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), Delhi, India, 2019.
  9. Lavanya ; JVR Ravindra, “Performance Metrics of Imprecise Multipliers Based on Proximate Compressors for IIR Filters”, in proceedings of 30th IEEE International Conference on Microelectronics (ICM), Sousse, Tunisia, Dec. 2018.
  10. Lavanya Maddisetti ; JVR Ravindra, “Performance Metrics of Inexact Multipliers Based on Approximate 5:2 Compressors” in proceedings of IEEE International SoC Design Conference (ISOCC),
  11. Sai Satyanarayana Reddy ; J.V.R. Ravindra ; N. Hanuman Reddy ; Anji Reddy Polu, “A Novel Nanocomposite Polymer Electrolyte for Application in Solid State Lithium Ion Battery” In proceedings of IEEE 18th International Conference on Nanotechnology (IEEE-NANO), Cork, Ireland, June 2018
  12. Padmini C and J.V.R.Ravindra ” PEARL: Performance Analysis of Ultra Low Power Reversible Logic Circuits against DPA Attacks ” in proceedings of International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) – 2016, Chennai, TN, India. (10.1109/ICEEOT.2016.7755539)
  13. Padmini C and J.V.R.Ravindra ” CALPAN: Countermeasure Against Leakage Power Analysis Attack by Normalized DDPL” in proceedings of 6th IEEE International Conference on Circuits, Power and Computing Technologies (ICCPCT-2016), Kanyakumari, TN, India, 2016.                     (DOI 10.1109/ICCPCT.2016.7530142)
  14. SrimaiInapurapu, J.V.R.Ravindra ” NEON: Near-Accurate Efficient FIR Filter for Ultra Low-Power Applications” in proceedings of IEEE 20th International Conference on Applied Electronics, Pilsen, Czech Republic, 2016. (10.1109/AE.2016.7577250)
  15. Chiranjeevi S, J.V.R.Ravindra ” A Novel and Efficient Design of Golay Encoder for Ultra Deep Submicron Technologies”, in proceedings of IEEE 6th International Conference on Advances in Computing, Communications and Informatics, Jaipur, India, pp. 275- 280, 2016. (10.1109/ICACCI.2016.7732059)
  16. J.V.R.Ravindra “Towards Improving Accuracy of Nonlinear Time Invariant VLSI Circuits Using Volterra Series Based Parametric Analysis” in proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, South Korea, 2016. (10.1109/APCCAS.2016.7803983)
  17. Sangeeta Singh, JVR Ravindra and B RajendraNaik “Power and Area Calibration of Switch Arbiter for High Speed Switch Control and Scheduling in Network-on-Chip”n Proceedings of IEEE International Conference on SOC (ISOCC 2016), November 23-26, 2016, Jeju, South Korea. (10.1109/ISOCC.2016.7799765) (Received IEEE/IEIE Best Paper Award)
  18. J.V.R.Ravindra ” CCSDR: Design of Ultra Low Power FFT Processor using Novel Conditional Canonic Sign Digit Representation” in proceedings of IEEE 20th International Conference on Applied Electronics, Pilsen, Czech Republic. pp. 89-92, Sep 7-8, 2015.
  19. SrimaiInapurapu, J.V.R.Ravindra, S. Sai Satyanaraya Reddy, “JARVIS: Just-Accurate Competent IIR Filter Using Proximate Reversible Adder for Low-power Applications” in proceedings of IEEE 7th International Conference on Computational Intelligence, Modelling and Simulation (CIMSim 2015), Kuantan, Malaysia, 27 – 29 July 2015. (DOI 10.1109/CIMSim.2015.25) 2005-2014
  20. Mosin Abdul, J.V.R.Ravindra “A Novel Polynomial Basis Multiplier for Arbitrary Elliptic Curves over GF (2^m)”, in proceedings of IEEE International Conference on Convergence of Technology (I2CT-2014), Pune, MH, India, 2014, pp.1-3. (DOI: 10.1109/I2CT.2014.7092022)
  21. R. Gangadhar Reddy, J.V.R.Ravindra ”A Novel Power-Aware and High Performance Full Addrer Cell for Ultra-Low Power Designs ”, in proceedings of IEEE International Conference on Circuits, Power and Computing Technologies (ICCPCT-2014), Kanyakumari, TN, India, 2014, PP. 1121-1126 (DOI: 10.1109/ICCPCT.2014.7055037)
  22. N. Sainath Reddy, J.V.R.Ravindra, ”A Novel Modulo 2^n+1 Fused Multiply-Adder unit for secured VLSI architectures ”, in proceedings of IEEE International Conference on Circuits, Power and Computing Technologies (ICCPCT-2014), Kanyakumari, TN, India, 2014, pp. 1302-1306 (DOI: 10.1109/ICCPCT.2014.7055038)
  23. R. Gangadhar Reddy, J.V.R.Ravindra, K.Harikrishna “Design of Ultra Lowpower Full Adder using Modified Branch Based Logic Style” In proceedings of IEEE 7th European Modelling Symposium on Mathematical Modeling and Computer Simulation, Manchester, UK, 20-22 Nov, 2013. pp. 650-655, (DOI 10.1109/EMS.2013.116)
  24. K. Narasimha Rao, J.V.R.Ravindra, Y. Pandurangaiah ” Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology” In proceedings of IEEE 7th European Modelling Symposium on Mathematical Modeling and Computer Simulation, Manchester, UK, 20-22 Nov, 2013. pp. 656-659.(DOI 10.1109/EMS.2013.117)
  25. J.V.R.Ravindra, Y.PanduRangaiah, L.V.N Prasad, ” A Novel Analytical Model for Analysis of Delay and Crosstalk in Non Linear RLC Interconnects for Ultra Low Power Applications” in proceedings of IEEE International Conference on Modeling and Simulation, (UKSim-2013), Cambridge, United Kingdom, April 10-12, 2013. (DOI 10.1109/UKSim.2013.143)
  26. J.V.R.Ravindra, M.B.Srinivas. ” Performance modeling of high speed VLSI interconnects”, in proceedings of Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics 2010 (PrimeAsia’10), September 22-24, Shanghai, China.  (DOI: 10.1109/PRIMEASIA.2010.5604960)
  27. J.V.R.Ravindra, M.B.Srinivas, “Efficient Model Order Reduction Technique using Subspace Iteration Scheme for Linear Time-Varying RLC Circuits” in proceedings of 11th Euromicro Conference on Digital System architectures, Methods and Tools (DSD 2008), September 3-5, 2008, University of Parma, Parma, Italy.
  28. J.V.R.Ravindra, M.B.Srinivas, “Reduced-order Modeling of High Speed VLSI Interconnects using Static Superelement Technique for Nano Meter Designs” in proceedings the IEEE/ACM International Symposium on Nanoscale Architectures (NANO-ARCH), June 12-13, 2008, Anaheim, CA, USA. (Co-located with the 45th Design Automation Conference (DAC 2008))
  29. J.V.R.Ravindra, M.B.Srinivas, “Static Superelement Technique based Model Order Reduction for High Speed Nanometer Designs” in proceedings of the 8th IEEE International Conference on Nanotechnology (IEEE NANO), Aug 18-21, 2008, Texas, USA. (DOI: 10.1109/NANO.2008.223)
  30. J.V.R.Ravindra, M.B.Srinivas, “Generating Reduced Order Models for High Speed VLSI Interconnects using Balancing-Free Square Root Method” in proceedings of 12th IEEE Workshop on Signal Propagation on Interconnects (SPI 2008). May 12-15, 2008 Avignon, Popes Palace, France. (IEEE Computer Press).
  31. J.V.R.Ravindra, M.B.Srinivas, “Generic Sub-Space Algorithm for Generating Reduced Order Models of Linear Time Varying VLSI Circuits”, in proceedings of 18th ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 111-114, May 4-6, 2008.
  32. J.V.R.Ravindra, M.B.Srinivas, \Modeling of Full-Wave High Speed on Chip RLC Interconnects using Frequency Shift Technique” in proceedings of 9th IEEE Electronics Packaging Technology Conference (EPTC 2007), December 10-12, 2007.
  33. J.V.R.Ravindra, M.B.Srinivas, \Model Order Reduction for RLC Interconnects using Response Dependent Condensation” IEEE Region 10 conference TENCON 2007, October 30- November 2, Taipei, 2007.
  34. S. Sainarayanan, C. Raghunandan, J. V. R. Ravindra, M. B. Srinivas, “Bus Coding to Minimize Redundant Bit Transitions” IEEE Region 10 Conference TENCON 2007, October 30- November 2, Taipei, 2007.
  35. J.V.R.Ravindra, Sandeep Saini, Avinash Shukla, M.B.Srinivas, “Sign Extension Based Method Low Power Fast Fourier Transform” in Proceedings of IEEE International Conference on SOC (ISOCC 2007), October 17-19, 2007.
  36. J.V.R.Ravindra, M.B.Srinivas, \Response Dependent Condensation Based macromodeling for Linear Time Varying High Speed VLSI Interconnects” in Proceedings of 7th IEEE International Symposium on Communications and Information Technologies (ISCIT 2007), October 16-19, 2007.
  37. J.V.R.Ravindra, Sandeep Saini, M.B.Srinivas, “A Low- Power, High Speed, Asynchronous VLSI Architecture for FIR Filters”, in proceedings 13th IEEE International Symposium Integrated Circuits (ISIC 2007), September 26-28, Singapore, 2007. (Accepted but not Published)
  38. J.V.R.Ravindra, M.B.Srinivas, “Generating Reduced Order Models using Subspace Iteration for Linear RLC Circuits in Nanometer Designs” in ACM SIGARCH /SIGMICRO 2nd International Conference on Nano-Networks (Nano-Net 2007), September 24-26, 2007.
  39. J.V.R.Ravindra, M.B.Srinivas ‘Modeling and Analysis of Crosstalk for Distributed RLC Interconnects using Di.erence Model Approach”, ACM SIGDA 20th Symposium on Integrated Circuits and System Design (SBCCI 2007), September 3-6, pp. 207-211, September, 2007, Copacabana, Rio de Janeiro, Brazil.
  40. J.V.R.Ravindra, M.B.Srinivas, ‘Model Order Reduction Techniques for Nonlinear and Time Varying High Speed RLC Interconnects” session on Work in Progress (WiP) 2007, In connection with 10th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2007), pp. 18-19, August 27 – 31, 2007, Lubeck, Germany.
  41. J.V.R.Ravindra, M.B.Srinivas, “A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects”, in proceedings of 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), pp. 325-330, August 27 – 31, 2007, Lubeck, Germany.
  42. S.Sainarayanan, J.V.R.Ravindra, C Raghunandan and M B Srinivas, “Coupling Aware Energy-E.cient Data Scrambling On Memory-Processor Interfaces,” in 2nd IEEE International Conference on Industrial and Information Systems (ICIIS 2007), August 8-11, 2007, University of Peradeniya, Srilanka.
  43. J.V.R.Ravindra, M.B.Srinivas, “Delay and Skew Analysis of VLSI Interconnects using Difference Model Approach” in Joint Conference on 50th IEEE Mid West Symposium on Circuits and Systems (MWSCAS) and 5th North East Symposium on Circuits and Systems (NEWCAS 2007), August 5-8, 2007, Montreal, Canada.
  44. J.V.R.Ravindra, M.B.Srinivas, “Analytical Crosstalk Model with Inductive Coupling in VLSI Interconnects” in proceedings of 11th IEEE Workshop on Signal Propagation on Interconnects (SPI 2007) May 13-16, 2007 Ruta di Camogli (Genova), Italy.
  45. J.V.R.Ravindra, NavyaChittravu, M. B. Srinivas, “Energy Efficient Spatial Coding Technique for Low Power VLSI Applications” The 2006 International Workshop on System-on-Chip (IWSOC-2006), Dec 27-29, 2006.
  46. S.Sainarayanan, J.V.R.Ravindra, Kiran T. Nath, M.B.Srinivas, “Coding for Minimizing Energy in VLSI Interconnects” in Proceedings of 18th IEEE International Conference on Microelectronics (ICM 2006), pp. 166-169, 16-19 December, Dhahran, Saudi Arabia.
  47. S.Sainarayanan, C.Raghunandan, J.V.R.Ravindra, M.B.Srinivas, “Efficient Spatial-Temporal Coding Schemes for Minimizing Delay in Interconnects” in Proceedings of IEEE TENCON 2006, pp. 515-518, 14-17 November, Hong Kong.
  48. S.Sainarayanan, C.Raghunandan, J.V.R.Ravindra, M.B.Srinivas, “Modified Area Efficient Temporal Coding Technique for Delay Minimization on VLSI Interconnects” in proceedings of IEEE International Conference on SOC (ISOCC- 06). October 2006, Seoul, Korea.
  49. J.V.R.Ravindra, K. S. Sainarayanan, M. B. Srinivas, “A Novel Low Power Bus Encoding Technique for Minimizing RGB Transitions for LCD Display of Digital Camera” 10th IEEE VLSI Design and Test Symposium 2006 (VDAT-2006) pp. 205-214, August 9 -12, 2006, Goa, India.
  50. S. Sainarayanan, J.V.R.Ravindra, M. B. Srinivas “A Low Power Overhead Bus Coding Technique for Minimizing Inductive Crosstalk in VLSI Connectors” SIGDA 15th Inter. Workshop on Logic & Syn. (IWLS), June 7-9, 2006, Vail, Colorado, USA.
  51. S. Sainarayanan, J.V.R.Ravindra, M. B. Srinivas, “A Novel Coupling Driven Low Power Bus Coding Technique for Minimizing capacitive Crosstalk in VLSI Interconnects”, IEEE International Symposium on Circuits and Systems (ISCAS- 2006), pp 4155-4158, May 21-24, 2006, Island of Kos, Greece.
  52. S. Sainarayanan, J.V.R.Ravindra, M. B. Srinivas, “Minimizing Simultaneous Switching Noise (SSN) using Modi.ed Odd/Even Bus-Invert Method” In 3rd IEEE International Workshop on Electronic Design, Test and Applications(DELTA- 2006), January 2006.
  53. J.V.R.Ravindra, K. S. Sainarayanan, M. B. Srinivas, “An Efficient Power Reduction Technique for Low Power Data I/O for Military Applications”, In Proc of 24th Digital Avionics Systems Conference, October 2005.
  54. S. Sainarayanan, J.V.R.Ravindra, M. B. Srinivas, “A Novel Deep Sub-micron Low Power Bus Coding Technique”, In Proc. of International Association of Science and Technology for Development. October 2005.
  55. S.Sainarayanan, J.V.R.Ravindra, M.B.Srinivas, “An Efficient Power Reduction Technique for Low Power Data I/O Using Gray Code” in proceedings of IEEE International Conference on Applied Electronics (AE-2005), pp 289-292, September 2005, Pilsen, Czech Republic.
  56. J.V.R.Ravindra, K. S. Sainarayanan, M. B. Srinivas, “EDGE: Encoding and Decoding of Generic Data for Minimizing Switched Capacitance and Transition Density for Low Power VLSI Applications” In IEEE International Conference on SOC. October 2005.
  57. J.V.R.Ravindra, K. S. Sainarayanan, M. B. Srinivas, “A Novel Bus Coding Technique for Low Power Data Transmission” In IEEE Symposium on VLSI Design and Test Conference (VDAT-2005), pp 263-266, August 2005.

Books Published:

  1. Signals and Systems—SPITECH Publishers (2004)
  2. TV Engineering – SPITECH Publishers (2002)

Research Projects Undertaken:

Completed Projects:

  1. (04/13 — 03/16): All India Council for Technical Education (AICTE): Design, Development and Analysis of Routing Algorithms for Wireless Sensor Networks: Applications in Environment Monitoring and Disaster Relief.
  2. (09/15 — 08/20): Department of Science and Technology (DST): Fund for Improvement of S&T Infrastructure in Higher Educational Institutions (FIST), to establish Humanoid Robotics Lab.
  3. (02/16 — 01/19): Cognitive Science Research Initiative, Department of Science and Technology (CSRI–DST): SAMSED — Smartening and Monitoring the Environment using Ad-hoc Wireless Sensor Networks for Disaster Survivor Detection.
  4. (05/16 — 04/19): WOSA- DST, Differential Power Attacks.

Patents:

  1. Indian Patent (File No: 201641001617) JVR Ravindra, Srimai.I, “A Novel Graphics Compatible Adder (GCA) for Digital Displays, Devices and Systems”