Dr. S. Karunakaran

Faculty Id: VCE 1041
Date of Birth: 17 May , 1980
Designation: Professor
Years of Experiance : 13
Email Id: nskarunakharan@gmail.com
Phone Number: 7339658532
Faculty Web Page:
Employment Status: Full Time - Ratified by JNTUH
Areas of Specialization: Low Power VLSI Design, High Performace VLSI Architecture for DSP Applications, ASIC Design
UG Degree: B.E (Electrical and Electronics Engineering),2002,Periyar University,Salem
PG Degree: M.E (VLSI Design),2007, Anna University,Chennai
Ph.D: VLSI Design 2015 ,Anna University,Chennai
Subjects Taught:
  1. VLSI Design Techniques
  2. ASIC Design
  3. Low Power VLSI Design
  4. VLSI Technology
  5. Linear Integrated Circuits
  6. Electronic Devices and Circuits
  7. Biomedical Instrumentation
  8. Electromagnetic Fields
  9. Electrical Machines
Papers Published:
  1. S.Karunakaran,Y.Pandurangaiah,Joseph Anthony Prathap,B.Poonguzharselvi"Exploration On Power Delay Product Of Various Vlsi Multiplier Architectures"International Journal of Mechanical Engineering and Technology(IJMET), Jan 2018,ISSN Print:0976-6340,ISSN Online:0976-6359.
  2. Naveen Kishore Gattim,Karunakaran S ,”Multimodal Image Fusion Using Curvelet and Genetic Algorithm, Journal of Scientific & Industrial Research Vol. 76, November 2017, pp. 694-696 (Accepted for publication).
  3. Karunakaran S , Naveen Kishore Gattim ,”VLSI Implementation of folded FIR filter structures using high speed multipliers”Journal of Engineering and Applied Sciences.(Accepted for Publication).
  4. Karunakaran, S “Investigations on the performance of the basic logic gates for various CMOS logic structures”, National conference on Emerging trends in Electronics and Computer Applications, Oct 20-21,2016 at Srinidhi Institute of Science and technology, Hyderabad.
  5. Karunakaran, S“Exploration on power delay product of basic logic gates for various CMOS logic styles”, International Journal of Engineering Studies. Volume 9, Number 2 (2017), pp. 111-120.
  6. Karunakaran, S ,“VLSI Architecture of an 8 bit multiplier using Vedic Mathematics in 180 nM technology”, International Journal of Advances in Engineering & Technology ,June 2017 .
  7. Karunakaran S, Rukmanidevi, S 2015,’Low latency and less power dissipation of a 4:2 compressor based distributed arithmetic unit FIR filter design’, International Journal of Applied Engineering Research, vol. 10,no. 9 pp. 23465-23477.
  8. Karunakaran S, Kasthuri, N 2012, ‘VLSI Implementation of FIR Filter Using Computational Sharing Multiplier Based On High Speed Carry Select Adder”, American Journal of Applied Sciences, vol. 9, no. 12, pp. 2028-2045.
  9. Karunakaran S, Kasthuri, N 2012, ‘High Performance VLSI Architecture for FIR filter Using On-the-Fly Conversion Multiplier’, European Journal of Scientific Research, vol. 67, no. 4, pp.625-635.
  10. Karunakaran S, Kasthuri, N 2011, ‘Area and Power Efficient VLSI Architecture for FIR filter using Asynchronous Multiplier’, British Journal of Science, December, vol. 2, no. 2, pp. 61-77.
  11. Karunakaran S ,Gowrisankar ,V ’High speed VLSI Architecture for distributed Arithmetic FIR filter using compressors’International conference on CSCT presented on 5th May 2010 at Einstein college of Engineering ,Tirunelveli
  12. Karunakaran S, Murugesan,G, Premkumar,P, “Design of Power Efficient Folded FIR Filter Structures using Modified Booth Recoding Multiplier” International Conference on CSCT presented on 8th May 2010 at Cape Institute of Technology,Tirunelveli.
  13. Karunakaran S, Nidhin Joe Kuttikat “VLSI Implementation of Adaptive FIR filter using distributed arithmetic”National Conference on CI presented on 4th April 2009.
  14. Karunakaran S, Arun C., Muthukumaran S. and Rajamani V., ‘Low Power VLSI Architecture for Viterbi Decoder’, 2 nd National Conference on TICAE-07, Presented on 15th -17th March 2007, Sathyabama University, Chennai.
Books Published:
Research Projects Undertaken: