Prof. S. Rajendar

Faculty Id: VCE 054
Date of Birth: 04 December , 1980
Designation: Professor
Years of Experiance : 14
Email Id: s.rajendar@vardhaman.org
Phone Number: 9885570842
Faculty Web Page: http://vardhaman.org/faculty-freshman-engineering.html
Employment Status: Full Time - Ratified by JNTUH
Areas of Specialization:

Low Power and High-performance VLSI Circuit Design.

Interconnect Modeling and Optimiation.

UG Degree: B. Tech (Electronics and Communication Engineering),2003,JNTU, Hyderabad
PG Degree: M. Tech (Digital Systems and Computer Electronics),2009, JNTU, Hyderabad
Ph.D: Electronics and Communication Engineering (Pursuing) ,JNTU, Hyderabad
Subjects Taught:

UG :

  1. Electronic Devices and Circuits
  2. Electronic Circuit Analysis
  3. Control Systems
  4. Linear IC Applications
  5. Digital IC Applications
  6. VLSI Design
  7. Digital Design through Verilog HDL
  8. Basic Electrical Engineering
  9. Microprocessors and Interfacing

PG :

  1. Digital System Design
  2. VLSI Technology and Design.
  3. Algorithms for VLSI Design Automation
Papers Published:

Journals:

  1. M Nagarjuna,D. Mahesh Babu,S. Rajendar"Novel Low Power Design Techniques of Read-Out Path Circuit in a Register File"Journal of Electron Devices Vol. 23, Num. 1, 2016, pp 1927-1933, ISSN:1682 -3427 (print), ISSN:1682 -3427.

  2. Dr. R. Murali Prasad, Mr. S. Rajendar “A Novel Power Efficient On-Chip Test Generation Scheme for Core Based System-On-Chip (Soc) “, Journal of Theoretical and Applied Information Technology. ISSN: 1992-8645, 30th Nov 2015. Vol.81. No.3, Pp 433-437
  3. Mr S. Rajendar, R. Murali Prasad, A Novel Power Efficient On-Chip Test Generation Scheme for Core Based System-On-Chip (Soc)”, Journal of Theoretical and Applied Information Technology 30th November 2015. Vol.81. No.3, ISSN: 1992-8645 Pp 433-437
  4. Mr. S. Rajendar,” Modeling And Design of Energy Efficient SRAM Cell For Embedded Memory Architecture”, International Journal of Advances In Engineering & Technology. ISSN: 2231-1963, Vol. 8, Issue 4, Aug 2015, Pp-637-645.
  5. Mr. S. Rajendar, Mr. C. Lokanath Reddy,” Design Of Low Power Transposition RAM Using Optimized Memory Primitives”, International Journal of Electronics & Communication Technology, ISSN: 2230-7109, Vol. 6, Issue 3, July-Sept 2015, PP: 78-82.

  6. S. Rajendar, P. Chandrasekhar, M. Asha Rani, Ambati Divya, “A Novel Low Power Swing Limited Repeater Insertion Technique for On-Chip Interconnects”, International Journal of VLSI Design and Communication Systems (VLSICS), Vol. 5, No. 6, December, 2014, pp 63-73, eISSN : 0976-1357, ISSN (Print) : 0976-1527, DOI:10.5121/vlsic.2014.5607.
  7. Kothagudem. Mounika,S. Rajendar, R. Naresh, “A Charge Recycling Three Phase Dual-Rail Pre-charge Logic Based Flip-Flop”, International Journal of VLSI Design and Communication Systems (VLSICS), Vol. 5, No. 6, December, 2014, pp 35-42, eISSN : 0976-1357, ISSN (Print) : 0976-1527, DOI:10.5121/vlsic.2014.5605.
  8. M. Nagarjuna, M. Narendra Reddy,S. Rajendar, “Integration of Bus Specific Clock Gating and Power Gating”, International Journal of Computer Applications Technology and Research, e-ISSN: 2319-8656, Volume 3, Issue 11, November, 2014, pp 745-750.
  9. S. Rajendar, P. Chandrasekhar, M. Asha Rani, P. Pradeep Kumar Reddy, “Energy Efficient Design of Static Asymmetric Low Swing On-Chip Interconnect Circuits” International Journal of Computer Applications (0975 – 8887), Volume 80, No. 15, October 2013, pp 33-35, DOI: 10.5120/13940-1927.
  10. G. Mareswara Rao,S. Rajendar, “Design of Low Power Pulse Triggered Flip-Flop Using Self Driven Pass Transistor Logic”, International Journal of Computer Applications (0975 – 8887), Volume 80, No. 15, October 2013, pp 9-12, DOI: 10.5120/13935-1886.
  11. V. Harini,S. Rajendar, "Design, Validation and Correlation of Characterized SODIMM Modules Supporting DDR3 Memory Interface", IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278-2834, p-ISSN: 2278-8735. Volume 6, Issue 5 (Jul. - Aug. 2013), pp 01-11, DOI: 10.9790/2834-0650111.
  12. B.U.V. Prashanth, C. Padmini,S. Rajendar, “Design and Implementation of a Floating Point ALU on STRATIX – III FPGA”, International Journal of Computer Applications (0975 – 8887), Volume 55, No. 2, October 2012, pp 48-50, DOI: 10.5120/8731-2610.


Conferences:

  1. S. Rajendar,Pasula Ramakrishna"A Novel High Performance Design of Memory Architecture Using Modified 4T CAM Cell"IEEE international Conference on Inventive Communication and Computational Technologies (ICICCT 2017), 10-11 March 2017, Coimbatore, India

  2. S. Bhargavi,S. Rajendar"Design of a Parallel Self-Timed Adder by Using Transmission Gate Logic Style"4th IEEE International Conference on Advanced Computing and Communication Systems (ICACCS - 2017), 06-07 Jan 2017, Coimbatore, India.

  3. Pasula Ramakrishna,S. Rajendar,Nagarjuna Malladhi"Design of Low Power Memory Architecture Using 4T Content Addressable Memory Cell"4th IEEE International Conference on Advanced Computing and Communication Systems (ICACCS - 2017), 06-07 Jan 2017, Coimbatore, India.

  4. Mr. S. Rajendar, Mr. P.Chandrasekhar, Mrs. Asha Rani, “Performance Analysis of Alternate Repeaters For On-Chip Interconnections In Nanometer Technologies”, Elsevier 2rd International Conference on Nonmaterial’s And Technologies (CNT 2014), 2015, PP-344-352.
  5. Mr. S. Rajendar, Mr. S. Srinivas, “Power-Aware Alternative Adder Cell Structure Using Swing Restored complementary Pass Transistor Logic At 45nm Technology”, Elsevier 2rd International Conference on Nonmaterial’s And Technologies (CNT 2014), 2015, PP-789-792.
  6. Mr S. Rajendar, “Design of Low Power Adaptive Pulse Triggered Flip-Flop Using Modified Clock Gating Scheme At 90nm Technology”, Elsevier 2rd International Conference on Nonmaterial’s And Technologies (CNT 2014), 2015, PP-1-8.
  7. Kavali Krishna,S. Rajendar, P. Vamshi Bhargava “A Novel Low Power Double Edge Triggered Flip-Flop Based on Clock Gated Pulse Suppression Technique”, IEEE International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO – 2015), 24-25, January 2015.
  8. T. Bhagyalaxmi,S. Rajendar, S. Srinivas, “Power-Aware Alternative Adder Cell Structure using Swing Restored Complementary Pass Transistor Logic at 45nm Technology”, 2ndInternational Conference on Nanomaterials and Technologies, CNT – 2014, 17-18, October 2014, Published in Elsevier Procedia Material Science.
  9. S. Rajendar,P. Chandrasekhar, M. Asha Rani, R. Naresh, “Performance Analysis of Alternate Repeaters for On-Chip Interconnections in Nanometer Technologies”, 2ndInternational Conference on Nanomaterials and Technologies, CNT – 2014, 17-18, October 2014, Published in Elsevier Procedia Material Science.
  10. Kavali Krishna,S. Rajendar, R. Naresh, “Design of Low Power Adaptive Pulse Triggered Flip-Flop Using Modified Clock Gating Scheme at 90nm Technology”, 2ndInternational Conference on Nanomaterials and Technologies, CNT – 2014, 17-18, October 2014, Published in Elsevier Procedia Material Science.
  11. Thonta Bhagyalaxmi,S. Rajendar, Y. Pandu Rangaiah, “Performance Analysis of Alternate Adder Cell Structures Using Clocked and Non-Clocked Logic Styles at 45nm Technology”, IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI – 2014), September 24-27, 2014,Greater Noida, India.
  12. S. Rajendar, P. Chandrasekhar, M. Asha Rani, “A Novel Sleep Transistor Based Differential Current Sensing Amplifier for On-Chip Interconnects”, Proceedings of International Conference on Photonics, VLSI and Signal Processing, ICPVS 2014, 28-29, March 2014, Kakatiya University, Warangal, India.
  13. N. Umamaheshwar Rao,S. Rajendar, S. Srinivas, “Design of Integrated Multi-band Antenna for Wireless Communication Networks”, ELSEVIER Proceedings of International Conference on Photonics, VLSI and Signal Processing, ICPVS 2014, ISBN – 978-93-5107-228-7, 28-29, March 2014, Kakatiya University, Warangal, India.
  14. T. Bhagyalaxmi, Y. Pandu Rangaiah,S. Rajendar, “Power and Delay Analysis of Full-Adder Cell Structures in Deep Submicron CMOS Technology”, Proceedings of International Conference on Photonics, VLSI and Signal Processing, ICPVS 2014, 28-29, March 2014, Kakatiya University, Warangal, India.
  15. G. Mareswara Rao,S. Rajendar, “Design of Low Power Pulsed Flip-Flop using Sleep Transistor Scheme”, Proceedings of IEEEInternational Conference on Advances in Electrical Engineering, ICAEE 2013, ISBN: 978-1-4799-2465-3, December 21-23, 2013, Independent University, Bangladesh.
  16. S. Rajendar, P. Chandrasekhar, M. Asha Rani, “Study of Crosstalk Noise and Delay Modeling for RC On-chip Interconnects”, National Conference on Nanomaterials and Technologies, CNT 2013, 15 – 16 February 2013, Hyderabad. ISBN 978-93-5126-236-7
  17. S. Rajendar, M.P.Sireesha, T. Ramakrishnaiah, N. Satyanarayana, “Study of Comparative Delay Analysis of Conventional Copper Interconnects and CNT Interconnects”, National Conference on Nanomaterials and Technologies, CNT 2013, 15 – 16 February 2013, Hyderabad. ISBN 978-93-5126-236-7
  18. G. Kalyan Chakravarthy, M. Nagarjuna,S. Rajendar, “Reduction of Soft Error Tolerance using ABMM”, International Conference on Electronics and Communication Engineering, ICIECE – 2012 during July 20-21, 2012 at Gurunanak Institutions, Hyderabad.
  19. S. Rajendar, Arvind Chary, “Modified Glitch Free Adiabatic Circuit Design Approach for Low Power Applications”, National Conference on Signal Processing and Embedded System Applications, (COSMOS – 2011) organized by CMR College of Engineering, Hyderabad, during 8-10, July 2011.
  20. S. Rajendar, K. Abhishek, “Schmitt Trigger Insertion for High Performance and Low Power VLSI Interconnects”, National Conference on Signal Processing and Embedded System Applications, (COSMOS – 2011) organized by CMR College of Engineering, Hyderabad, during 8-10, July 2011.
  21. Shruthi Divya,S. Rajendar, “VLSI Implementation of Parallel and Asynchronous Decoder for Wireless Communication Applications” Presented in the National Conference on Signal Processing and Embedded System Applications, (COSMOS – 2011) organized by CMR College of Engineering, Hyderabad, during 8-10, July 2011.
  22. A. Priyanka,S. Rajendar, “Design and Implementation of Digital Down Converter for Software Defined Radio” Presented in the National Conference on Signal Processing and Embedded System Applications, (COSMOS – 2011) organized by CMR College of Engineering, Hyderabad, during 8-10, July 2011.
  23. S. Rajendar, Anees Pasha, “Improved Frequency Domain Receiver Algorithm for LTE SC FDMA Based Uplink MIMO System” Presented in the National Conference on Signal Processing and Communications, (SPCOM – 2010), organized by Malla Reddy College of Engineering, during 23-24, December 2010.
  24. I. Pavani Prapurna,S. Rajendar, “Spread Spectrum Based Spatial Domain Invisible Watermarking Algorithm for Still Images”, Proceedings of National Conference on Signal Processing and Communications, (SPCOM – 2010), organized by Malla Reddy College of Engineering, during 23-24, December 2010.
  25. S. Rajendar, B.K.Madhavi, Y. Rajasekhar Reddy, “Analysis of CMOS Steady State Non Ideal Electrical Behavior of Coupled VLSI Interconnects”, Proceedings of National Conference on Recent Trends in Communication Technologies & VLSI Design (RTCTV – 2010) organized by the Department of ECE and R&D Center of Vardhaman College of Engineering, during 2 – 3 June 2010.
  26. S. Srinivas, N. Umamaheshwar Rao,S. Rajendar, “FPGA Implementation of Matched Filter Based DSSS Digital GPS Signal Receiver” Proceedings of National Conference on Recent Trends in Communication Technologies & VLSI Design (RTCTV – 2010) organized by the Department of ECE and R&D Center of Vardhaman College of Engineering, during 2 – 3 June 2010.
  27. M. V. Sireesha, G. Vinod Reddy,S. Rajendar, “FPGA Implementation of Time Sliced Multichannel UART Core to Reduce CPU Overhead”, Proceedings of National Conference on Recent Trends in Communication Technologies & VLSI Design (RTCTV – 2010) organized by the Department of ECE and R&D Center of Vardhaman College of Engineering, during 2 – 3 June 2010.
  28. S. Rajendar, Y. Pandu Rangaiah, “Circuit Model Simulation of Carbon Nanotube Bundles for VLSI Interconnects and Vias”, Proceedings of National Conference on Nanomaterials, Applications and Nanotechnology Developments (NAND – 2009) organized by R & D Department of Vardhaman College of Engineering, during 4 – 5 September 2009.
Books Published:
  1. Y Pandu Rangaiah,S Rajendar, “Electronic Devices and Circuits”, Spectrum University Press, Students Helpline Publishing House (P) Ltd., Hyderabad, 2013.
  2. S. Rajendar, Y. Pandu Rangaiah, “Electronic Devices”, Spectrum Techno Press, Students Helpline Publishing House (P) Ltd., Hyderabad, 2013.
Research Projects Undertaken:
None