Dr. D. Ajitha

Faculty Id: VCE 1208
Date of Birth: 10 June , 1974
Designation: Associate Professor
Years of Experiance : 15
Email Id: ajithavijay1@vardhaman.org
Phone Number: 9490486349
Faculty Web Page:
Employment Status: Full Time - Ratified by JNTUH
Areas of Specialization: VLSI
UG Degree: Electronics and Communication Engineering,2006,JNTUH
PG Degree: VLSI System Design,2009, JNTUA
Ph.D: ECE 2017 ,JNTUA
Subjects Taught:

UG:

  1. Digital Logic Design
  2. Micro Processors and Interfacing
  3. Micro Processors and Microcontrollers
  4. Switching Theory and Logic Design
  5. Computer Organization
  6. Electronic Devices and Circuits
  7. Digital IC Applications
  8. VLSI Design
  9. Electronic Measurements and Instrumentation
  10. Digital Design through Verilog HDL

PG:

  1. Digital IC Design
  2. Hardware Software Co-Design
  3. Testing & Testability
  4. ASIC design
Papers Published:

Journal Publications

  1. D.Ajitha, An Enhanced High Speed Multi-Digit BCD Adder using Quantum-dot Cellular Automata–Journal of Semiconductors-Scopus Indexed-Thomson Reuters-Web of Science. Vol. 38, No. 2, February 2017, pp 1-9. Impact Factor : 0.5.
  2. Ajitha, D., K. Venkata Ramanaiah, and V. Sumalatha. “ An Optimized Hybrid Multi-Digit BCD Adder Using QCA” International Journal of Computer Science and Information Security, Vol. 14, No. 7, July 2016, pp 589-598. (Emerging Sources Citation Index (ESCI)-IP & Science-Thomson Reuters-Web of Science). Impact Factor : 0.519.
  3. D.Ajitha, A.Harika “Area Efficient Digital Logic Circuits Based On 5-Input Majority Gate Using QCA” International Journal of Computer Science and Information Security, Vol. 14, No. 6, June 2016, pp 589-598. (Emerging Sources Citation Index (ESCI)-IP & Science-Thomson Reuters-Web of Science).Impact Factor : 0.519.
  4. Ajitha, D., K. Venkata Ramanaiah, and V. Sumalatha. "An Efficient Design Of XOR Gate And Its Applications Using QCA." i-Manager's Journal on Electronics Engineering Vol. 5, No. 3 (March-May 2015), pp.22-29. Global Impact Factor : 0.765.
  5. H.Uma Maheswari, D.Ajitha, “A comparative analysis of electronic and molecular quantum dot cellular automata.” in AIP Conference Proceedings 1665, (59th DAE Solid State Physics Symosium organized by BARCat VIT) 050073 (2015); doi: 10.1063/1.4917714.
  6. H.Uma Maheswari, D.Ajitha,V.Sumalatha, 2013, “Quantum Dot Cellular Automata-The Endowement For Modern Computing.” in International Journal of Engineering Sciences Research(IJESR),ISSN:2230-8504;e-ISSN–2230-8512,Volume 4-Special Issue 01,.pp:1174-1178.
  7. D.Ajitha,K.N.Chandra sekhar, K.Venkata Ramanaiah, V.Sumalatha, November -2013 “Design of Compact and High Speed Baugh–Wooley Multiplier By CSA Using QCA” in International Journal of Engineering Research & Technology (IJERT), ISSN : 2278-0181,Volume 2-Issue 11, pp:2162-2167.
  8. D.Ajitha, P.Yugesh Kumar, K.Venkata Ramanaiah, V.Sumalatha, November-2013 “Efficient Design of 2’s Complement Adder/Subtractor Using QCA” in International Journal of Engineering Research & Technology (IJERT), ISSN : 2278-0181,Volume 2-Issue 11, pp:3049-3054.

IEEE International Conferences

  1. Dharmavaram Asha Devi, D. Ajitha and Arvind Ramshetty “Design and Implementation of Power Efficient Digital Clock Using FPGA” in IEEE International Conference on Microelectronic Devices, Circuits and Systems (ICMDCS’17), 11-12th August 2017, VIT University, Vellore.

  2. D. Ajitha, K.Venkata Ramanaiah, V. Sumalatha, “Hybrid Single-Digit BCD Adder using Quantum-dot Cellular Automata" Proceedings of the IEEE Student Conference on Research and Development (SCOReD 2015), 13-14th December 2015, pp 629-632, Kuala Lumpur, Malaysia. (Scopus Indexed) (Best Paper Award).

  3. D.Ajitha, K.Venkata Ramanaiah,V.Sumalatha, “A Novel Design of Cascading Serial Bit-Stream Magnitude Comparator Using QCA” in IEEE International Conference on Advances in Electronics, Computers and Communications (ICAECC-2014 ), 10th & 11th October,2014. pp 1-6, Bangalore.

  4. Krishna MV, Ajitha D. Network on chip for data packet exchange, IEEE International Conference in Science Engineering and Management Research (ICSEMR), Nov 27 2014 (pp. 1-4).

  5. D. Ajitha, K. Venkata Ramanaiah, and V. Sumalatha. "Design of High Speed, Low Area, Carry Flow BCD Adder in QCA." Proceedings of the IEEE International Conference on Advanced Research in Engineering and Technology (IEEE ICARET), vol. 8, 8-9th February 2013, pp 510-514, Vijayawada.

Books Published:
None
Research Projects Undertaken:
None