Dr. P. Kalyani
Date of Birth:
12 January, 1986
Areas of Specialization :
Low Power VSI
Ph.D. in LOW POWER VLSI 2020, JNTU Hyderabad
M.Tech in VLSI System design,2010, CVR College of Engineering
B.Tech in Electronics and Communication Engineering,2007, Scient Institute of Technology, Hyderabad
VLSI System Design, Digital design through Verilog, Digital image processing, CPLD &FPGA Architectures and Applications, Signals and Systems, Pulse and Digital Circuits, Electronic Circuit Analysis, Antenna and Wave Propagation.
- Kalyani , Dr. M.Madhavi Latha and P. Chandra Sekhar, “Energy efficient SRAM Cell design with Body biasing ” , Vol . 64, Lecture Notes in Network and Systems, Springer, 2018.(SCOPUS)
- Kalyani , Dr. M.Madhavi Latha and P. Chandra Sekhar, “ Analysis of MOS transistor behavior with Forward and Reverse Body biasing in Subthreshold region”, International Journal of Applied Engineering Research( IJEAR), Vol 13, Number 19, pp. 14236-14240, 2018. (UGC Journal).
- Kalyani , Dr. M.Madhavi Latha and P. Chandra Sekhar, “Power gating and Body biasing Techniques to reduce Power ”, in International Journal of Emerging Technology and Advanced Engineering (IJETAE), Vol. 7,Issue.1 ,pp. ,Dec 2017(UGC Journal)
- Kalyani, Y. Rachana, R. Soumya, M. Veeranna, “High Speed Low Power MAC Design using Parallel Adders and Multipliers International Journal for Scientific Research & Development (IJSRD), Vol 7, Issue 2,ISSN(O) 2321-0613, pp. 1812-1814, 2019.
- Kalyani, S. Sai kiran reddy, S. Jyothsna, V. Bharadwaj , “IOT based agricultural robot for cultivation, seeding and irrigation”, International Journal For Research & Development in Technology (IJRDT), Vol 11, Issue 4,ISSN(O) 2349-3585, pp. 359-362, Apr-2019.
- Thudimilla Sadhana , P.Kalyani , Dr. D. NageshwarRao , “ VLSI based Signal Processing Solution for Calculation of Sidelobe Amplitude in Pulse Compression”, in International Journal of Engineering Trends and Applications (IJETA), 4,Issue. 6,pp. 33-38,Nov-Dec 2017.
- Jhansi Rani , S. Sai Sree Andal , P. Kalyani, “Carry Select Adder design using Brent Kung Adder”, in International Journal of Engineering Trends and Applications (IJETA), Vol. 4,Issue. 6,pp. 50-53,Nov-Dec 2017
- Kalyani, Sneha and Dr. D. Nageswar Rao, “High Speed Low Power MTCMOS D-Latch Based 32-Bit Carry Select Adder using 10-TFull Adder”, in Int. Journal of VLSI system design and communication systems (IJVDCS),Vol. 4,Issue. 10,pp. 1066-1069,oct 2016.
- Kalyani, Dr. P. Satish kumar and Dr. K. Ragini, “Various Low Power Techniques for CMOS Circuits”, in Int. Journal of Engineering Research and Applications(IJERA),Vol. 3,Issue. 6,pp. 330-333,Dec 2013.
- Kalyani, “Low Power Design for CMOS Circuits”, in CVR JOURNAL OF SCIENCE & TECHNOLOGY, Vol. 1,pp. 29,Dec 2012.
- Kalyani, P. Satish kumar and P. Chandra Sekhar, “Design of Subthreshold Adiabatic Logic based Combinational and Sequential Circuits”, in proc of IEEE Conf. International Conference On Emerging Trends and Innovation(ICEI),Feb 3-5,2017,Pune.
- Kalyani, P. Satish kumar and P. Chandra Sekhar, “Energy Efficient Logic Gates Using Subthreshold Adiabatic Logic”, in proc of IEEE Conf. International Conference on Inventive Computation Technologies ( ICICT),Aug 26-27,2016,Coimbatore.
- P.Kalyani, Dr. P. Satish kumar and Dr. K. Ragini, “Multi-Purpose Inverter Circuit for Low Power Digital Applications”, in National Conference NCVSComs-13,pp. 108-112,2013.
Research Projects Undertaken: