Dr. S. Karunakaran

Date of Birth:
17 May , 1980
Areas of Specialization :
Low Power VLSI Design, High Performace VLSI Architecture for DSP Applications, ASIC Design
Qualification:
Ph.D in VLSI Design-Faculty of Information and Communication Engineering,2015, Anna University,Chennai
PG Degree in M.E (VLSI Design),2007, Anna University,Chennai
UG Degree in B.E (Electrical and Electronics Engineering),2002,Periyar University,Salem.
Subjects Taught:
VLSI Design Techniques, ASIC Design, Low Power VLSI Design, VLSI Technology, Linear Integrated Circuits, Electronic Devices and Circuits, Biomedical Instrumentation, Electromagnetic Fields, Electrical Machines.
Papers Published:
Journals:
- Karunakaran, T.Logeswaran, S.Shruti, R.Shravya, Thota Kavya “Performance Analysis of ALU design using Irreversible and Reversible gates” International Joural of Advanced Science and Technology, Volume 29 Issue (7s) P.no 4168-4173, June 2020”
- Karunakaran, B.Poonguzharselvi “High Performance VLSI Architecture for Braun Multiplier” International Journal of Innovative Technology and Exploring Engineering (IJITEE) , Volume-8 Issue-10, August 2019
- Karunakaran and B.Poonguzharselvi “Investigations on power dissipation of low power VLSI architectures for Voltage level shifters” Jour of Adv Research in Dynamical & Control Systems, Vol. 11, Special Issue-05, 2019
- Karunakaranand Naveen Kishore Gattim” VLSI Implementation of Folded FIR filters using High Speed Multipliers” Journal of Engineering and Applied Sciences Vol 14 issue 4 ; pp 1070-1077 ,2019.
- Jaiganesh, P. Arulkumar, S.Karunakaran, Md. Asif, N. Srinivas “Improving the Efficiency of Solar Photovoltaic Cell by Decreasing Surface Temperature” International Journal of Engineering and Advanced Technology (IJEAT) , Volume-9 Issue-2, December, 2019
- Fatima Unnisa, K.Jaiganesh, P.Arulkumar, S.Karunakaran “Direct Coupled PV Panel with ĆUK Converter for DC Load Applications” International Journal of Innovative Technology and Exploring Engineering (IJITEE) , Volume-9 Issue-2, December 2019.
- Karunakaran, B.Poonguzharselvi,M.Narayana “Analysis of Low Power VLSI Design of Adder Cells” Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018
- Karunakaran , Boddupally Harshitha , B.Poonguzharselvi , K.Jai Ganesh “Exploration of power delay product [PDP] on feedback based dual edge triggered flip flop utilizing dual sleep and dual slack approach” International Journal of Engineering & Technology, 7 (4) (2018) 3388-3391
- Karunakaran,Y.Pandurangaiah,JosephAnthonyPrathap,B.Poonguzharselvi “Exploration On Power Delay Product of Various VLSI Multiplier Architectures” International Journal of Mechanical Engineering and Technology(IJMET), Volume 9, Issue 1, January 2018, pp. 53–59
- Karunakaran, N K Gattim “Multimodal Image fusion using curvelet and genetic algorithm” Journal of Scientific and Industrial Research, Vol 78, Nov 2017, pp 694-696
- Karunakaran “Exploration on power delay product of basic logic gates for various CMOS logic styles”, International Journal of Engineering Studies. Volume 9, Number 2 (2017), pp. 111-120.
- Karunakaran,“VLSI Architecture of an 8 bit multiplier using Vedic Mathematics in 180 nM technology”, International Journal of Advances in Engineering & Technology ,June 2017 .
- Karunakaran, Rukmanidevi, S 2015,’Low latency and less power dissipation of a 4:2 compressor based distributed arithmetic unit FIR filter design’, International Journal of Applied Engineering Research, vol. 10,no. 9 pp. 23465-23477.
- Karunakaran, Kasthuri, N 2012, ‘VLSI Implementation of FIR Filter Using Computational Sharing Multiplier Based On High Speed Carry Select Adder”, American Journal of Applied Sciences, vol. 9, no. 12, pp. 2028-2045.
- Karunakaran, Kasthuri, N 2012, ‘High Performance VLSI Architecture for FIR filter Using On-the-Fly Conversion Multiplier’, European Journal of Scientific Research, vol. 67, no. 4, pp.625-635.
- S.Karunakaran, Kasthuri, N 2011, ‘Area and Power Efficient VLSI Architecture for FIR filter using Asynchronous Multiplier’, British Journal of Science, December, vol. 2, no. 2, pp. 61-77.
Conferences:
- Karunakaran “Investigations on the performance of the basic logic gates for various CMOS logic structures”, National conference on Emerging trends in Electronics and Computer Applications, Oct 20-21,2016 at Srinidhi Institute of Science and technology, Hyderabad.
- Karunakaran,Gowrisankar ,V ’High speed VLSI Architecture for distributed Arithmetic FIR filter using compressors’ International conference on CSCT presented on 5th May 2010 at Einstein college of Engineering ,Tirunelveli
- Karunakaran, Murugesan,G, Premkumar,P, “Design of Power Efficient Folded FIR Filter Structures using Modified Booth Recoding Multiplier” International Conference on CSCT presented on 8th May 2010 at Cape Institute of Technology,Tirunelveli.
- Karunakaran, Nidhin Joe Kuttikat “VLSI Implementation of Adaptive FIR filter using distributed arithmetic” National Conference on CI presented on 4th April 2009.
- S.Karunakaran, Arun C., Muthukumaran S. and Rajamani V., ‘Low Power VLSI Architecture for Viterbi Decoder’, 2 nd National Conference on TICAE-07, Presented on 15th -17th March 2007, Sathyabama University, Chennai.
Books Published:
None
Research Projects Undertaken:
None