Mr. R. Phani Vidyadhar

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Department:
Electronics & communication Engineering
Faculty Id:
VCE741
Designation:
Assistant Professor
Vidwan-ID:
241999
Years of Experience:
6 years
Employment Status:
Full Time – Ratified by JNTUH
DOJ:

09/12/2013

JNTU ID:

16150331-230354

Years of Industry Experience:

Nil

Years of Research Experience:

Nil

Ph.D. Guide:

No

Number of PhDs Awarded under your supervision:

NA

Number of PhD scholars, Currently Supervising:

NA

Number of Patents Published:

Nil

Number of Patents Granted:

Nil

AICTE ID:

1-2190513245

Phone:
8801333811

Date of Birth:

19 May ,1989

Areas of Specialization :

VLSI Design Automation, DSP, ASIC Design

 

Qualification:

PG Degree in  B.TECH,2011,JNTU
UG Degree in M.TECH(VLSI Design),2013, SRM

Subjects Taught:

Signals and systems, Digital Signal Processing, Digital logic Design.

Papers Published:

  1. R.Phani Vidyadhar and J.Selvakumar,”Reconfigurable Architecture using fast heuristic algorithm for integer arithmetic”,IRD2013 Conf.Proceedings,ISBN:978-93-81693-88-14,MARCH,2013.
    R.Phani Vidyadhar and J.Selvakumar,”Reconfigurable Architecture using fast heuristic algorithm for integer arithmetic”IJAEEE Journal Publication ,ISSN-2278-8948.
    R.Phani Vidyadhar and J.Selvakumar “FPGA IMPLEMENTATION OF RECONFIGURABLE ARCHITECTURE FOR LOGICAL OPERATRIONS “,IJECE JOURNAL PUBLICATION ,ISSN-2278-9901 HAVING IMPACT FACTOR(JCC)-2.593.

Books.Published:

None

Research Projects Undertaken:

None