Date of Birth:

19 January , 1986

Areas of Specialization :

VLSI

Qualification:

PG Degree in  M.Tech (VLSI System Design),2013, TKR College of Engg & Tech, JNTU,
UG Degree in B.Tech (Electronics and Communication Engineering),2007,Aurora’s Technological Research Institute, JNTUH

Subjects Taught:

Electronic Devices and Circuits, Electronic Circuit Analysis, VLSI Design.

Papers Published:

1. Lavanya Maddisetti , Ranjan K. Senapati , JVR Ravindra” Training Neural Network as Approximate 4:2 Compressor applying Machine Learning Algorithms for Accuracy Comparison” International Journal of Advanced Trends in Computer Science and Engineering,Volume 8, No.2, March – April 2019,pp.221-225.
2. Lavanya Maddisetti, Ranjan Senapati, JVR Ravindra, “Supervised Machine Learning for Training a Neural Network as 5:2 Compressor,” International Journal of Innovative Technology and Exploring Engineering, Vol(8), Issue(10), 2019.Indexed in: Scopus, Google ScholarIndexed in: Scopus, Google Scholar
3. Lavanya, M, RanjanK. Senapati, JVR Ravindra, “Low-Power Near-Explicit 5:2 Compressor for Superior Performance Multipliers”, International Journal of Engineering Research and Technology, Vol (11), No.(4), 2018.
4. M.Lavanya, “Gate Count Comparison of different 16-bit Carry Select Adders” ,International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering ,vol.3,Issue 7,July 2014. DOI:10.15662/ijareeie.2014.0307034
5. Lavanya .M, D. Nageshwar Rao, K. RamaKrishna Reddy, “Design of Low power 16-bit carry select adder using 0.18um technology” ,International Journal of Computer Applications,Paper Reference ID:pxc3900863.

Conferences:

1. Lavanya Maddisetti, JVR Ravindra, “Low-Power. High-Speed Adversarial Attack based 4:2 Compressor as Full Adder for Multipliers in FIR Digital Filters”, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS), 29-30 Oct. 2019, Helsinki, Finland.
2. Lavanya Maddisetti, JVR Ravindra, “Machine Learning based Power Efficient Approximate 4:2 Compressors for Imprecise Multipliers”, 32^nd International Conference on VLSI Design (VLSID), January 2019, New Delhi, India.
3. Lavanya Maddisetti, JVR Ravindra, “Performance Metrics of Inexact Multipliers Based on Approximate 5:2 Compressors”, International SOC Design Conference (ISOCC), November 2018, Daegu, South Korea.
4. M, JVR Ravindra, “Performance Metrics of Imprecise Multipliers Based on Proximate Compressors for IIR Filters”, International Conference on Microelectronics (ICM), December 2018, Sousse, Tunisia.
5. Won “certificate of Best paper” in an International conference, ICIECE-2013.

Books Published:

None

Research Projects Undertaken:

None