Mr. Nagarjuna Malladhi

Department:
Electronic & Communication Engineering
Faculty Id:
VCE 482
Designation:
Assistant Professor
Years of Experience:
8 years 5 months
Employment Status:
Full Time – Ratified by JNTUH
Phone:

Date of Birth:

11 July , 1988

Areas of Specialization :

VLSI Design

 

Qualification:

PG Degree in M. Tech (Electronic and Communication Engineering),2011, Vignan University, Vadlamudi
UG Degree in B. Tech (Electronic and Communication Engineering),2009,JNTU, Kakinada

Subjects Taught:

 

Journals:

  1. M Nagarjuna,D. Mahesh Babu,S. Rajendar”Novel Low Power Design Techniques of Read-Out Path Circuit in a Register File”Journal of Electron Devices Vol. 23, Num. 1, 2016, pp 1927-1933, ISSN:1682 -3427 (print), ISSN:1682 -3427.
  2. Mr. M. Nagarjuna,Mr. S. Rajendar,Mr. C. Lokanath Reddy,” Novel design techniques of read out path circuit in low power register file”, International journal of advanced information science and technology.ISSN: 2319-2682, vol.43, no.43, November 2015.pp: 41-47.
  3. M. Nagarjuna, B. Narendra Reddy, S, Rajendar, “Integration of Bus Specific Clock Gating and Power Gating”, International Journal of Computer Applications Technology and Research, Volume 3– Issue 11, 745 – 750, 2014.
  4. M. Varun, M. Nagarjuna, M. Vasavi, “Design of High Speed Modulo 2n+1 Adder”, International Journal Computer Applications, Volume 81 – No 17, November 2013.
  5. K. Sridhar Reddy, M. Nagarjuna, H. Shravan Kumar, “An Efficient Low Power Viterbi Decoder Design Using T – algorithm”, International Journal Computer Applications, Volume 76 – No 5, August 2013.
  6. G. Kalyan Chakravarthy, Nagarjuna M, V Ramakrishna, “A Novel Bus Encoding Scheme for Reducing Switching Activity in VLSI Interconnects”, International Journal of Communication Applications, pp.484 – 487, 2012.

Conferences:

  1. G. Kalyan Chakravarthy,J. Krishna Chaithanya,M. Nagarjuna“Necessity of FDP’s for engineering education”Fourth International Conference on Transformation in Engineering Education in association with IUCEE at VCE, Hyderabad, Jan 04 – 06, 2017, pp. 83 – 84, ISBN – 978-93-82829-49-2.
  2. Pasula Ramakrishna,S. Rajendar,Nagarjuna Malladhi“Design of Low Power Memory Architecture Using 4T Content Addressable Memory Cell”4thIEEE International Conference on Advanced Computing and Communication Systems (ICACCS – 2017), 06-07 Jan 2017, Coimbatore, India.
  3. Mr. I. Babu, Mrs. Sangeetha Singh, Mr. Nagarjuna, Mr. B. Swarna Kishore, “Cost Reduced Techniques For Floor planning With Whitespace Rectilinear Block Using B*-Tree”, 3rd International Conference on Electrical, Electronics, Engineering Trends, Communication, Optimization and Sciences (EEECOS)-2016.
  4. Nagarjuna M, “Reed Solomon Error Correcting Codes using FPGA”,National Conference on Advanced Computing and Communications(NCACC-2011).
  5. G Kalyan Chakravarthy, Nagarjuna M, S Rajendar, “Reduction of Soft Error Tolerance Using ABMM”, International Conference on Innovation in Electronics and Communication Engineering (ICIECE – 2012).
  6. M. Nagarjuna, S. Srinivas, H. Shravan Kumar, M. Veeraswamy, “Design of High Performance soft error tolerance latch for Nanoscale CMOS technology”, National Conference on Nanomaterials & Technologies 2013, pp. 69 – 77.
  7. M. Nagarjuna, V. Harini, A. Vijayalakshmi, M. Ramanjaneyulu, “Efficient Multiternary Digit Adder Design in CMOS Technology”,National Conference on Nanomaterials & Technologies 2013, pp. 87 – 94.

Books Published:

None

Research Projects Undertaken:

None