Mr. R. Phani Vidyadhar
Date of Birth:
19 May ,1989
Areas of Specialization :
VLSI Design Automation, DSP, ASIC Design
PG Degree in B.TECH,2011,JNTU
UG Degree in M.TECH(VLSI Design),2013, SRM
Signals and systems, Digital Signal Processing, Digital logic Design.
R.Phani Vidyadhar and J.Selvakumar,”Reconfigurable Architecture using fast heuristic algorithm for integer arithmetic”,IRD2013 Conf.Proceedings,ISBN:978-93-81693-88-14,MARCH,2013.
R.Phani VidyadharÂ and J.Selvakumar,”Reconfigurable Architecture using fast heuristic algorithm for integer arithmetic”IJAEEE Journal Publication ,ISSN-2278-8948.
R.Phani VidyadharÂ and J.Selvakumar “FPGA IMPLEMENTATION OF RECONFIGURABLE ARCHITECTURE FOR LOGICAL OPERATRIONS “,IJECE JOURNAL PUBLICATION ,ISSN-2278-9901 HAVING IMPACT FACTOR(JCC)-2.593.
Research Projects Undertaken: