Ms. C. Padmini

Department:
Electronic & Communication Engineering
Faculty Id:
VCE 443
Designation:
Assistant Professor
Years of Experience:
15 years
Employment Status:
Full Time – Ratified by JNTUH
Phone:

Date of Birth:

21 March , 1979

Areas of Specialization :

Digital systems and Computer Electronics, Hardware Cryptography, Side Channel Attacks

 

Qualification:

Ph.D. in Electronics and Communication Engineering (Pursuing) ,J N T U, Hyderabad
PG Degree in M. Tech (Digital Systems and Computer Electronics),2011, JNT University, Anantapur
UG Degree in B. Tech (Electronics and Communication Engineering),2002,M.V.S.R college of Engineering, Osmania University, Hyderabad

Subjects Taught:

Electronic Devices and Circuits,Electronics Circuit Analysis,Integrated Circuits and Applications,Electromagnetic theory and Transmission Lines,Antenna Wave Propagation,Digital Communication,Information Theory and Coding,Optical Fiber Communications, Optical Networks

Papers Published:

  1. Padmini. C and J.V.R.Ravindra”PEARL: Performance Analysis of Ultra Low Power Reversible Logic Circuits against DPA Attacks” in proceedings of International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) – 2016, Chennai, TN, India.(10.1109/ICEEOT.2016.7755539)
  2. Padmini. C and J.V.R.Ravindra”CALPAN: Countermeasure Against Leakage Power Analysis Attack by Normalized DDPL” in proceedings of 6th IEEE International Conference on Circuits, Power and Computing Technologies(ICCPCT-2016),Kanyakumari, TN, India, 2016.(DOI 10.1109/ICCPCT.2016.7530142)
  3. Prof. J.V.R.Ravindra, Ms. Padmini Cheerla, Ms.Krishna Kumara Tummula, “Performance Analysis of Ultra Low Power Reversible Logic Circuits For Security Applications”, Proceedings of IEEE Region 10 Conference (IEEE-TENCON), University of Macua, Coati Stip Macau, Nov 1-4, 2015.
  4. Ms. C. Padmini” Enhanced Delay-Based Dual-Rail Pre charge Logic Against Leakage Power Analysis Attack”, International Journal of Current Engineering And Technology.ISSN: 2277 – 4106, aug 2015, Vol.5, No.4, PP-2800-2803.
  5. Prashanth B U V, C.Padmini, S.Rajendar, “Design and Implementation of a Floating Point ALU on a Stratix – III FPGA”, International Journal of Computer Applications, DOI: 10.5120/8731-2610 Vol 55, Issue 2, October, 2012.
  6. C.Padmini, G.Bhaskar Phani Ram, Venkat B Prashanth, “An Innovative VLSI algorithm Design Technique to reduce Leakage Current in CMOS VLSI Circuits”, International Journal of Advances in Electrical & Electronics Engineering, ISSN: 2319-1112, Vol 1, Issue 2, October, 2012.
  7. Venkat B Prashanth, C Padmini, Eliyaz Mohammed, G Bhaskar Phani, ” Wireless Measurement system using Zigbee Transmission implemented on TES” , International Journal of Advances in Electrical & Electronics Engineering, ISSN: 2319-1112, Vol 2, Issue 1.
  8. C. Padmini, Ch.Tejdeep “Design and Implementation of Microcode based Built-in Self-Test for Fault Detection in Memory and its Repair”, International Journal of Computer Applications, DOI: 10.5120/13519-1299, Volume 78 – No.9, September 2013.
  9. Koppula.Jagadeesh, C.Padmini “An Efficient Intruder Avoidance Method for MANETs”, International Journal of Computer Applications (0975 – 8887) DOI: 10.5120/18143-9379 Volume 103 – No.14, October 2014.
  10. K.Madhuri , C.Padmini, “A Secure Steganographic Technique for Embedding Text using Adaptive Pixel Pair Matching” GJRE Volume 14 Issue 6 Version 1.0, November 2014.

Books Published:

None

Research Projects Undertaken:

None